For example, a victim cache is disclosed in a patent reference 1 and a non-patent reference 1 as a technique for reducing cache misses.
FIG. 1 is a block diagram that shows a system example containing a victim cache in conventional technology. The system in the said diagram has a CPU 501, a cache memory 502, and a full associative type victim cache 503. The victim cache 503 has at least one entry that contains a tag address and line data.
When a cache miss occurs in the cache memory 502 and the victim cache 503, an oldest entry is selected in the cache memory 502 as a subject for replacement through LRU (Least Recently Used). Before the selected entry is replaced, contents of the concerned entry are transferred from the cache memory 502 to the victim cache 503. By doing so, entries in the victim cache 503 are updated. And after this, the selected entry in the cache memory 502 is replaced.
As a result, the victim cache 503 always holds at least a piece of line data that is discarded last time from the cache memory 502.
By doing so, when the CPU 501 accesses the data that is discarded from the cache memory 502 again, it is highly possible to hit it in the victim cache 503, which reduces penalties occurred by a cache miss.
Especially, for a case of accessing data closed in an extremely small area, which has an extremely strong temporal locality (a characteristic that accessed data tends to be accessed in the near future), is accessed intensively in an extremely short period of time, also has a strong spatial locality (a characteristic that adjacent data of accessed data tends to be accessed in the near future), the data originally held is likely to be held in the victim cache 503 while the data is being accessed so that it is highly effective to reduce penalties through a cache miss    Patent Reference 1: U.S. Pat. No. 5,261,066 Specification    Non-Patent Reference 1: Jouppi, N. P. [1990], “Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers, ”Proc. 17th Annual Int'l Symposium on Computer Architecture, 364-73